The invention relates to floating gate, nonvolatile, electrically alterable memory cells, and in particular to a memory cell with ultra-small dimensions and a method of making same.
Floating gate semiconductor nonvolatile memory cells, known as EEPROMs for electrically erasable programmable read only memories or EPROMs for erasable programmable read only memories, were invented over 30 years ago. They typically employ a very thin oxide window, i.e. a dielectric, in a MOS memory cell transistor to allow charge transfer through the thin window to and from between a drain or source electrode located in a substrate region and a floating gate located above the substrate. The floating gate is so named because it is not electrically connected to any electrode, but is surrounded by dielectric material, including the thin oxide window. This charge transfer phenomenon is a remarkable occurrence, called xe2x80x9ctunnelingxe2x80x9d, a quantum mechanical behavior in which electric charge passes through the thin dielectric oxide window to reach the floating gate but yet conduction in the usual meaning of that term, cannot occur in the dielectric material at the relatively low voltages under consideration. The logic state of the memory cell is determined by the presence or absence of charge on the floating gate which stores the charge until it is erased.
In U.S. Pat. No. 5,108,939, a floating gate region is formed in the conventional manner above a gate dielectric layer. The drain region is exposed utilizing photolithographic techniques and the gate dielectric removed. A thin layer of tunnel dielectric is then formed on the exposed drain region. A thin layer of polycrystalline silicon is then formed and etched in order to create very narrow floating gate extensions of polycrystalline silicon along the edge of the previously formed floating gate. The floating gate extension formed in this manner is separated from the drain region by thin tunnel dielectric. Another dielectric layer is then formed to provide a dielectric over the drain region which has a greater thickness than the tunnel dielectric underlying the floating gate extension. The patent teaches a method of self-aligning the tunnel oxide to the floating gate and achieving submicron dimensions for the tunnel oxide, i.e. less than the characteristic linewidth dimension of manufacturing equipment. U.S. Pat. No. 6,156,610 to P. Rolandi describes formation of a select transistor simultaneously with formation of an EEPROM structure.
In prior patent application Ser. No. 09/847,810 of B. Lojek, now U.S. Pat. No. 6,369,422, granted Apr. 9, 2002, assigned to the assignee of the present invention, there is disclosed a method of making a nonvolatile memory cell structures wherein the size of the thin oxide window remains finite, but the part of the oxide window through which charge is transferred may be reduced to a size smaller than the minimum feature size resolution of the manufacturing equipment being used. This is accomplished by positioning the fixed-size oxide window in such a manner that its size is limited and whose position controls the amount of charge allowed to be transferred through it. The oxide window is constructed such that a first part of it lays over only one part of the two opposing field oxide regions and its remaining part lies over the channel region of a MOS transistor, but does not extend across it. This effectively creates a slit and the size of the slit may be adjusted by moving the position of the oxide window. Parts of the oxide window constructed over the field oxide region cannot be used to allow charge transfer to the floating gate. Only the part of the oxide window that lies over the channel region may be used to permit such charge transfer. Thus, one can construct an effective charge transfer region that is quite small, i.e. smaller than the minimum feature size of manufacturing equipment. A thin window is constructed which overlaps the field oxide and does not reach across the width of the channel. In this sense the thin window is asymmetric since symmetric thin windows completely reach across the width of the channel.
While small transistor size-is possible with this construction, as the thin window becomes smaller, the window must be protected from process steps that might erode quality. An object of the invention was to devise a small size thin window, i.e. smaller than the feature size of manufacturing equipment, yet is constructed in a manner that protects the quality of the window.
The above object is achieved by establishing thin tunneling windows in an early stage of an EEPROM fabrication process. Presently, the minimal characteristic dimension of the process equipment is limited by the minimum dimension which can be made by the use of photolithography. The present invention creates a thin window having a length or width which is actually less than this characteristic dimension of the fabrication process.
A nitride mask over a gate oxide layer on a substrate is used to first create self-aligned source and drain regions for an EEPROM memory cell. The nitride mask protects the future channel which will exist between source and drain electrodes. After formation of source and drain, a second nitride layer is deposited in which nitride spacers are formed on either side of the nitride mask and etched to a desired dimension having a length whose length will be the dimension of the tunnel oxide. Gate oxide is removed on one side of the nitride mask so that the dummy spacer on this side can approach the substrate. This dummy spacer has no purpose except to define the length of the future tunnel oxide window. The size of the spacer is smaller than that which could be made by lithography, typically a fraction of one micron. A supplemental oxide deposition on the sides of the nitride forms an oxide nest with the nitride spacers within, in a sort of slot. When nitride is removed by an etching process, the nest is empty. The ability to etch a narrow nest or slot establishes the small dimension of the thin window to be formed in this space, rather than a reliance on photographic resolution in photolithography. Once the nitride spacer is removed, a layer of thin tunnel oxide is applied across the edge of the cell.
Where two cells are simultaneously formed in symmetric relation, the thin oxide can extend past the edge of the cell, across the edge of an adjacent cell and into a region formerly occupied by a dummy spacer in the adjacent cell. Such a thin oxide stripe, extending across two cells, does not interfere with the formation of the remainder of the two cells. For example, poly one is deposited across each cell and etched back to form a floating gate. Real nitride spacers may optionally be formed at edges of the poly one floating gate. Subsequent layers of oxide and poly two complete the cell structure. It should be noted that the real nitride spacers are not in the same position as the former dummy spacers, which have been lost to etching. The optional real spacers remain in place, protecting edges of the poly one floating gate from lateral mobile electron or ion migration into or out of the floating gate.
Select transistors may be formed simultaneously with EEPROM structures using selected layers and steps, such as the implantation step for source and drain formation, an oxide deposition step following nitride removal. This oxide deposition forms a gate oxide for the select transistor but forms an inter-poly oxide for the EEPROM devices. The oxide deposition is followed by poly-two layer deposition. The select and EEPROM transistors are now finished in the usual way.